This invention is generally related to inter-chip communication, and more particularly, to a communication protocol employed for rescheduling purposes to achieve communication at any frequency.
The evolution of sub-micron CMOS technology has steadily improved the performance of microprocessors. Quadrupling every three years, it has prompted the development of product chips having clock frequencies exceeding 500 MHz, even attaining, at least on an experimental basis, clock frequencies of the order of 1 GHz. It is highly desirable to have memories, such as Dynamic Random Access Memories (DRAM), characterized not only by their high density but also by their high performance. Synchronous DRAMs (SDRAMs) typically use a 3-stage pipelined architecture and a 2-bit pre-fetch architecture for a consecutive column burst operation provided with an internal burst address counter, improving the data rate to 125 Mb/sec per pin for prior generation 16 Mb memories. Thereafter, 64 Mb SDRAMs introduced an address incremented pipeline scheme, increasing the data rate to 150 Mb/sec per pin. Still after, 256 Mb SDRAMs resorted to a wave-pipeline scheme with first-in first-out (FIFO) circuitry, boosting the data rate to approximately 250 Mb/sec per pin. Taking a more drastic step, the 72 Mb RAM bus DRAM (RDRAM) employing an 8-bit pre-fetch and a protocol based design provided with RAM Bus-Signalling-Level (RSL) interfaces, achieve frequencies as high as 800 Mb/sec per pinxc3x9716 DQs, resulting in 1.6 Gb/sec.
As the speed of memories improves, it is particularly important to optimize the communication between the microprocessor and the memory. FIG. 1a shows a conventional system (100) that establishes communication between a driver chip (110) and a receiver chip (120). When operating in a memory read access mode, the driver chip (110) is the memory and the receiver chip (120) is the microprocessor. When operating in a memory write access mode, the driver chip (110) is the microprocessor and the receiver chip (120) is the memory. Practitioners will fully realize that when implementing an actual system, a controller is required to establish data communication between the chip (130), the driver chip (110) and the receiver chip (120).
The detailed operation of the system (100) is explained with reference to the timing diagram shown in FIG. 1b. For simplicity sake, the discussion that follows assumes a single data rate of communication synchronized to a reference clock (CLKREF). However, the inventive method to be described hereinafter is not limited to the configuration shown, but it also applies to a double data rate communication with or without source synchronization. The driver chip (110) outputs data in synchronism with CLKREF on the data bus (DQ) following an output latency (LATOUT), which is measured from the time an output event command is recognized. More particularly, the output event is recognized when an output command signal (CMDOUT) is at 0 at the leading edge of a reference clock (CLKREF). The data is outputted to the data bus (DQ) driven by clock CLKREF after a lapse of a predetermined number of clock cycles. This is defined as the output latency (LATOUT). The receiver chip (120) receives data from the data bus (DQ) after a lapse of the input latency (LATIN), which is defined as the number of clock cycles after an event command is recognized. More particularly, the input event is recognized when an input command signal (CMDIN) is at 0 at the leading edge of CLKREF. Input data is received from the data bus (DQ) in synchronism with CLKREF following a number of clocks cycles. This number is defined as the input latency (LATIN). The control chip (130) predetermines the output latency LATOUT as well as the input latency LATIN applicable to the driver chip (110) and the receiver chip (120) by following LATIN and LATOUT rules. The control chip (130) schedules the output command (CMDOUT) and the input command (CMDIN) to successfully establish communication between the driver chip (110) to the receiver chip (120). In an actual system, the control chip (130) is the memory controller. Scheduling data between LATOUT, LATIN, CMDIN, and CMDOUT follows certain rules of communication in synchronism with CLKREF, which are applicable to the transfer of data from the driver chip (110) to the receiver chip (120) via the data bus (DQ). By way of example, and still referring to the same timing diagram, the scheduling of CMDOUT and CMDIN is shown for LATOUT=2 and LATIN=1.5. Note that the output data from driver chip (110) is available at a time when the data input event for the receiver chip (120) is enabled, resulting in a successful data communication. As the chip-to-chip communication frequency increases, synchronization with the reference clock (CLKREF) becomes more difficult to achieve since the internal operation of the system is usually referenced by the same reference clock CLKREF.
FIG. 2 illustrates a first example showing a synchronization error (terr) applicable to the driver chip (110). The following example assumes an output latency LATOUT of 1, although LATOUT may take any value. Internal output event control signal (CTRLOUT) switches to 1 when the output event is recognized (i.e., when CMDOUT is detected at the leading edge of the CLKREF). The presence of detection logic delays the actual recognition by an amount of time t1. The output event is enabled by detecting the leading edge of CLKINT when CTRLOUT is at 1. The actual output is valid even after t2 as a result of the presence of the output logic. The internal event recognition and the output logic delays t1 and t2 cause the actual output to introduce a synchronization error terr with respect to CLKREF. To avoid the problem of terr shown in FIG. 2, a DLL (Delayed Locked Loop) has often been advantageously used to create a compensated internal clock version which leads the reference clock (CLKREF) by a negative time delay t2.
Still referring to driver chip (110) and with reference to FIG. 3, an example that uses the aforementioned DLL compensation shows an output being synchronized to the reference clock (CLKREF). Let it be assumed that the system output is enabled by the leading clock (CLKINT) which compensates for the error t2 when using DLL compensation. Because of this negative CLKINT compensation by t2 of CLKREF, after a time delay t2, the output successfully synchronizes to the reference clock (CLKREF). This DLL compensation works well at low frequencies ( less than 200 Mhz). However, as the clock frequency increases, a problem with the digital shift surfaces when CLKINT compensates for the lapse of t2 occurring prior to the output event recognition, causing a digital latency shift condition. FIG. 4 illustrates the problem which causes a digital latency shift. The output recognition event defined by the leading edge of the CTRLOUT occurs at a time subsequent to the target leading edge of CLKINT. Thus, the driver chip detects the next leading edge of the target leading edge of CLKINT. As a result, the output occurs exactly one clock cycle later than the target. This causes a digital latency shift or offset between the predetermined latency (LATOUT) and the actual latency (ALATOUT) Mathematically, a digital shift occurs when t1+t2 greater than =TREF, where TREF represents the CLKREF cycle time, as shown. Thus, the digital shift is cycle-time dependent, the cycle-time of the first digital shift occurring when TREF=(t1+t2). Multiple cycles of n digital shifts occur when t1+t2 greater than =nTREF, wherein n is an integer greater than or equal to 1 representing the number of digital shifts. Thus, n=1 results in a single digital shift, as described above. This problem causes multiple digital shifts for the predetermined latency (LATOUT) command when an output event is scheduled to occur at a predetermined latency following the command. The output command (CMDOUT) is synchronized to the reference clock (CLKREF), but the internal output event control signal (CTRLOUT) must be synchronized to the compensated clock (CLKINT). FIG. 5 illustrates an occurrence when there is no digital shift for the predetermined latency (LATOUT) of 3. Note that the example counts the number of clock cycles 1 of 3 for LATOUT=f 3, unlike previous examples. FIG. 6 illustrates an instance of a 2 cycle digital shift (terr=2) for the predetermined latency (LATOUT) of 3. The actual latency (ALATOUT) is now equal to 5 because of the digital shift (terr=2). If the actual latency (ALATOUT) is different from the predetermined latency (LATOUT), the driver chip (110) and the receiver chip (120) will not communicate successfully. A similar problem exists for a digital shift or multiple digital clock shifts for the receiver chip (120) when the DLL compensation for the internal clock (CLKINT) is applied to synchronize the data input with the reference clock (CLKREF).
FIG. 7a illustrates the problem of communication at the system level in synchronism with CLKREF, when a digital shift occurs in the driver chip (110) and the receiver chip (120). System (100) consists of a driver chip (110), a receiver chip (120) and a control chip (130). The goal is to successfully exchange data between the driver chip (110) and the receiving chip (120) at a system level, exactly the same as was shown in FIG. 1. The following discussion assumes for simplicity sake a single data rate communication without resorting to source synchronization. However, the invention to be discussed hereinafter is not limited to this configuration but is also applicable to a double data rate communication with and without source synchronization. Referring to FIG. 7b, let it be assumed that the output latency (LATOUT) and the input latency (LATIN) predetermined by control chip (130) are 2.0 and 1.5, respectively, for the driver chip (110) and the receiver chip (120). It is also assumed that driver chip (110) causes a digital shift by one clock, although the receiver chip (120) does not cause a digital shift. The actual latency (ALATOUT) for driver chip (110) is therefore 3.0, and the actual latency (ALATIN) for the receiver chip (120) is same as the LATIN, i.e., 1.5. The driver chip (110) outputs data to the data bus (DQ) once ALATOUT=3, which is measured from the time at which an output event command is recognized. More particularly, the output event is recognized when an output command signal (CMDOUT) is at low at the leading edge of the reference clock (CLKREF). The output data is driven to the data bus (DQ) while synchronization with CLKREF is achieved once the actual output latency ALATOUT=3. The receiver chip (120) receives data on the data bus (DQ) after LATIN=1.5 measured from the time at which an event command is recognized. More particularly, the input event is recognized when input command signal (CMDIN) is at 0 at the leading edge of the CLKREF. The input data is received from the data bus (DQ) while synchronization with CLKREF has been established after 1.5 clocks, to become the input latency (LATIN). The control chip (130) schedules the output command (CMDOUT) and the input command (CMDIN), assuming a predefined LATOUT of 1 out of 2.0 and LATIN of 1 out of 1.5. In an actual system, the control chip (130) is the memory controller. This causes a failure in communication because the data has not yet been outputted by the driver chip (110) at a time when the data is received by the receiver chip (120). This failure is due to a digital shift occurring in the driver chip (110). A similar problem is encountered if it is the receiver chip which causes a digital shift. Accordingly, there is a strong requirement to overcome all the digital shift problems not only at the chip level which includes driver chips, receiver chips, and the like, but also at the system level in order to achieve good communication even at high frequencies.
Accordingly, it is an object of the invention to achieve chip-to-chip communication using a rescheduling scheme to overcome a digital latency shift problem.
It is another object of the invention to provide a digital latency control method which automatically detects a digital problem, and reschedules at least one predetermined latency command either for a driver chip or for a receiver chip.
It is still another object of the invention to provide a circuit and a method for detecting a digital latency shift as part of the aforementioned rescheduling scheme.
It is another object of the invention to provide a circuit and a method for detecting any number of digital latency shifts at any frequency.
In a one aspect of the present invention, there is provided an electric system including: a driving circuit for outputting data to a bus, the driving circuit being responsive to a prescheduled data output command and to a predetermined data output latency; a receiving circuit for receiving the data from the bus, the receiving circuit being responsive to a prescheduled data input command and to a predetermined data input latency; and a scheduling circuit for rescheduling at least one of the prescheduled data output commands and the predetermined data output latency, one of the prescheduled data input commands and the predetermined data input latency, wherein the driving circuit and the receiving circuit are timed to communicate data correctly. A number of the digital latency shift can be automatically detected by a simple on-chip digital shift detection scheme. Optionally, the digital latency shift can be detected by an off-chip tester for the rescheduling scheme.